The continuing trend in the semiconductor and integrated circuit industries is to develop and manufacture smaller components. This trend has resulted in integrated circuits and semiconductor devices having higher density due to an increased number of components coexisting in smaller physical areas. This downsizing has directly affected the location, number, and size of bond pads for electrical connections for these devices.
Wire bonding techniques have been developed to accommodate smaller bond pad sizes as well as the stacking of multiple chips in an integrated circuit package. However, decreased size and fewer locations of bond pads on various layers of multiple chips presents a different bonding problem. There exists a need, therefore, for a reliable wire bonding method which provides wire bonds among chips on different layers of a stacked chip assembly, as well as for the resulting wire-bonded assembly.